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The PowerPC 970, PowerPC 970FX, PowerPC 970GX, and PowerPC 970MP, are 64-bit Power Architecture processors from IBM introduced in 2002. When used in Apple Inc. machines, they were dubbed the PowerPC G5. The 970 family was created through a collaboration between IBM and Apple.〔http://www.apple.com/pr/library/2003/jun/23pmg5.html〕 The project went under the codename GP-UL or Giga Processor Ultra Light, where Giga Processor was the codename for the POWER4 from which the core was derived. When Apple introduced the Power Mac G5, they stated that this was a five-year collaborative effort, with multiple future generations, but it was short-lived. Apple had to retract the promise to deliver a 3 GHz processor one year after its introduction, and IBM could never get the power consumption down far enough for these processors to fit into a portable computer. Apple only used three variants of the processor. IBM’s JS20/JS21 blade modules and some low-end workstations and System p servers are based on PowerPC 970. It is also used in some high end embedded systems like Mercury’s Momentum XSA-200. IBM is also licensing the PowerPC 970 core for use in custom applications. A common misconception is that the PowerPC 970 was the core in IBM's Xenon processor in Microsoft's Xbox 360, but this is false. That processor is using cores similar to the Power Processing Element (PPE) in the Cell microprocessor. == Design == The PowerPC 970 is a single core derivative of the POWER4 and can process both 32-bit and 64-bit PowerPC instructions natively. It has a hardware prefetch unit and a three way branch prediction unit. Like the POWER4, the front-end is nine stages long. The PowerPC 970 can fetch and decode up to eight instructions, dispatch up to five to reserve stations, issue up to eight to the execution units and retire up to five per cycle. The execution pipelines were lengthened compared to the POWER4 to achieve higher clock frequencies. It has eight execution units: two arithmetic logic units (ALUs), two double precision floating-point units, two load/store units and two AltiVec units.〔Halfhill, Tom R. (28 October 2002). "IBM Trims Power4, Adds AltiVec". ''Microprocessor Report''.〕 One of the AltiVec units executes integer and floating-point instructions, and the other only permute instructions. The latter has three subunits for simple integer, complex integer and floating-point instructions. These units have pipelines of varying lengths: 10 stages for simple integer and permute instructions, 13 stages for complex integer instructions and 16 stage for floating-point instructions.〔 The processor has two unidirectional 32-bit double data rate (DDR) buses (one for reads, the other for writes) to the system controller chip (northbridge) running at one quarter of the processor core speed. The buses also carry addresses and control signals in addition to data so only a percentage of the peak bandwidth can be realized (6.4 GB/s at 450 MHz). As the buses are unidirectional, each direction can realize only half the aggregate bandwidth, or 3.2 GB/s.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「PowerPC 970」の詳細全文を読む スポンサード リンク
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